The release of version 4.0 of the StreamDSP VITA 17.1 Serial Front Panel Data Port (sFPDP) IP core has been announced by StreamDSP, enabling support for the latest 40nm FPGA devices from Altera and Xilinx.
COLUMBUS, OH (PRWEB) JUNE 18, 2010
The StreamDSP sFPDP IP core is a fully-compliant implementation of the Serial Front Panel Data Port (sFPDP) communications standard, as defined by the VITA 17.1-2003 specification. With its latest release, StreamDSP has added support for new 40nm Altera and Xilinx FPGA devices. The following FPGA devices have now been fully verified and hardware tested with the StreamDSP sFPDP IP Core:
Altera Stratix-IV GX
Altera Arria-II GX
Altera Stratix-II GX
Altera Arria GX
Xilinx Virtex-6 LXT
Xilinx Virtex-5 LXT/FXT
Xilinx Virtex-4 FX
StreamDSP provides “ready-to-run” simulations, evaluations, and reference designs targeted to popular development boards for each of the supported FPGA families. This allows StreamDSP’s customers to quickly and easily verify proper operation both in simulation and on their chosen device family and greatly simplifies integration of the IP into their own systems.
To ensure the full compliance of the sFPDP IP with the VITA 17.1-2003 specification, StreamDSP puts each release through a rigorous acceptance testing procedure involving a suite of frame generation and verification tests as well as hardware interoperability tests with a wide range of existing Serial FPDP products. StreamDSP also performs in-depth bit-level protocol analysis with a Serial FPDP protocol analyzer from Absolute Analysis.
“Absolute Analysis plays a key role in our ability to develop, validate, and deploy Serial FPDP IP that we know our customers can rely on. We use the Investigator Series protocol analyzer in order to quickly identify and solve low-level protocol issues,” commented Greg Schueller, StreamDSP’s Director of Business Development. “When you’re operating at high bitrates, it can be extremely difficult to isolate the source of subtle protocol violations. The Absolute Analysis equipment gives us the ability to capture 100% of link traffic at the full serial line rate, up to 4.25Gbps. This kind of information can be invaluable when you’re trying to verify things like running disparity, error detection, link synchronization, and proper flow control,” added Greg.
The unique multi-vendor, multi-device support offered by the StreamDSP sFPDP IP core gives users the ultimate flexibility in FPGA system design. Designers can target any supported Xilinx and Altera FPGA device while maintaining a common user interface. “Unlike Xilinx’s Aurora protocol or Altera’s SerialLite protocol, our Serial FPDP IP doesn’t lock users into a particular FPGA vendor,” said Greg. “This gives our customers the freedom to choose the best device for their application and also allows existing designs to be easily migrated to more modern FPGA families. When you’re starting a new design, you don’t want your FPGA selection to be limited by the IP that you used in your last design.”
Greg Schueller, Director of Business Development
Tel. +1 (614) 934-1274
Fax. +1 (614) 934-1001
StreamDSP LLC, 4449 Easton Way, Suite 200, Columbus, OH, 43219, USA
More information about the Serial FPDP VITA 17.1 Standard can be found at https://www.vita.com
Information on Absolute Analysis is available at https://www.absoluteanalysis.com
For more specific information about StreamDSP’s IP products, please visit: https://www.streamdsp.com, or call (614) 934-1274.
About StreamDSP LLC
StreamDSP is an intellectual property (IP) company specializing in video, serial communications, and data storage solutions for Field Programmable Gate Array (FPGA) devices. Headquartered in Columbus, OH, StreamDSP has over 50 years of combined experience serving the military and commercial markets, and is focused on developing IP and providing custom design services for FPGAs.
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